When a chip component is mounted on a printed board, a method is typically used in which the chip component and the printed board are electrically connected through soldering. Further, in order to add a function to vary wiring pitches and a function to perform rewiring, an interposer may be placed between the chip component and the printed board. In general, different constituent materials are used for the printed board, the interposer and the chip component; accordingly, the magnitude of thermal expansion of these parts during a process or under use environment conditions differs from each other. Consequently, stress acts exclusively on solder joint portions in which the printed board, the interposer and the chip component are connected to each other through soldering; thus, poor connection caused by cracks or the like may occur. Therefore, there is a need for a structure which can release the stress acting on the solder joint portion.
Japanese Patent Laid-Open No. 2008-244311 (Patent Literature 1) discloses a technique for releasing this stress acting on the solder joint portion. A semiconductor package board described in Patent Literature 1 is characterized by including a first circuit conductive layer electrically connected to a semiconductor device, a second circuit conductive layer having a connecting terminal used for electrical connection with an external component, an insulating layer disposed between the first circuit conductive layer and the second circuit conductive layer, and a via which is a through hole in the insulating layer, used for electrical connection of the first circuit conductive layer and the second circuit conductive layer, and also characterized in that the insulating layer has a dual-layer structure, and Young's modulus of a second insulating layer disposed on the side of the second circuit conductive layer is smaller than that of a first insulating layer disposed on the side of the first circuit conductive layer.
Japanese Patent Laid-Open No. 2008-227020 (Patent Literature 2) discloses another example. In Patent Literature 2, an electronic component mounting structure is used in which an electronic component chip having a plurality of protrusion electrodes distributed on the whole mounting surface thereof is mounted via the protrusion electrodes on a substrate. An object of the invention is to release stress produced in the protrusion electrodes caused by temperature rise during the operation of the electronic component and thereby improve the reliability of the electronic component; and a disclosed solution is that the protrusion electrodes are arranged so that the distribution density of the protrusion electrodes becomes higher in a direction from the center to the outer side of the mounting surface of the electronic component chip. In Patent Literature 2, solder bump is given as an illustrative example of the protrusion electrode.
Japanese Patent Laid-Open No. 2008-205184 (Patent Literature 3) discloses a mounting structure in which a connecting terminal of a semiconductor device is electrically connected through a connecting member to a circuit board, and the connecting member has a conductive protrusion including a columnar portion, and the cross-sectional area of the columnar portion being the result of cutting the columnar portion by a plane parallel to the surface of the semiconductor device is smaller than the surface area of the connecting terminal of the semiconductor device. The circuit board and the semiconductor device are electrically connected through the conductive portion of the connecting member.